1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for reading and writing to a frame buffer at a high rate of speed.
2. History of the Prior Art
One of the significant problems involved in increasing the ability of desktop computers has been in finding ways to increase the rate at which information is transferred to an output display device. The various forms of data presentation which are presently available require that copious amounts of data be transferred. For example, if a computer output display monitor is operating in a color mode in which 1024.times.780 pixels are displayed on the screen and the mode is one in which thirty-two bits are used to define each pixel, then a total of over twenty-five millions bits of information must be transferred to the screen with each frame that is displayed. Typically, sixty frames are displayed each second so that over one and one-half billion bits must be transferred each second. This requires a very substantial amount of processing power. In general, the transfer of this data to the display slows the overall operation of the computer.
In order to speed the process of transferring data to the display, various graphics accelerating circuitry has been devised. This circuitry is adapted to relieve the central processor of the computer of the need to accomplish many of the functions necessary to the transfer of data to the display. Essentially, these graphics accelerators take over various operations which the central processor would normally be required to accomplish. For example, block transfers of data from one position on the screen to another require that each line of data on the screen being transferred be read and rewritten to a new line. Storing information within window areas of a display requires that data available for each window portion be clipped to fit within that window portion and not overwrite other portions of the display. Many other functions require the generation of various vectors when an image within a window on the display is cleared or moved. All of these operations require a substantial portion of the time available to a central processing unit. These repetitive sorts of functions may be accomplished by a graphics accelerator and relieve the central processor of the burden. In general, it has been found that if operations which handle a great number of pixels at once are mechanized by a graphics accelerator, then the greatest increase in display speed may be attained. This, of course, speeds the operations involved in the display of graphical material.
A problem which has been discovered by designers of graphics accelerator circuitry is that a great deal of the speed improvement which is accomplished by the graphics accelerator circuitry is negated by the frame buffer circuitry into which the output of the graphics accelerator is loaded for ultimate display on an output display device. Typically, a frame buffer offers a sufficient amount of random access memory to store one frame of data to be displayed. However, transferring the data to and from the frame buffer is very slow because of the manner in which the frame buffers are constructed.
Recently a new frame buffer has been designed which is especially adapted to operate at much higher speeds. Such a frame buffer is described in detail in U.S. patent application Ser. No. 08/145,355 entitled Frame Buffer System Designed For Windowing Operations, C. Priem et al, filed on even date herewith. Such a frame buffer provides very fast operations. It is, however, desirable to provide enhancements which accelerate the operation of this improved frame buffer and other frame buffers.